FPGA Engineer, Trading Desk

DRW is a technology-driven, diversified principal trading firm. We trade our own capital at our own risk, across a broad range of asset classes, instruments and strategies, in financial markets around the world. As the markets have evolved over the past 25 years, so has DRW – maximizing opportunities to include real estate, cryptoassets and venture capital. With over 1,000 employees at our Chicago headquarters and offices around the world, we work together to solve complex problems, challenge consensus and deliver meaningful results. It’s a place of high expectations, deep curiosity and thoughtful collaboration. 

We are currently seeking a FPGA and Software Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA designs.

Responsibilities: 

  • Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
  • Facilitate software integration efforts by developing new APIs and optimizing low level code.
  • Propose creative solutions to overcome FPGA/hardware/software limitations
  • Liaise directly with software and other design teams

Candidate Requirements: 

  • Bachelor’s degree or higher, Computer/Electrical Engineering or Computer Science with 3+ years of experience within the field
  • Solid Hardware Engineering experience with a focus on digital design for FPGAs or ASICs.
  • C++ expertise required
  • Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
  • Strong skills in RTL logic design (Verilog and System Verilog) and verification
  • Experience in FPGA design flow including synthesis, place & route, static timing analysis
  • Knowledge of UNIX operating systems and system performance concerns
  • Experience with multi-threaded programming and asynchronous frameworks
  • Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
  • In depth knowledge of the TCP/IP stack and on chip networking applications
  • Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
  • Excellent research and data gathering skills
  • Familiarity with higher level scripting languages such as Python and applications for automating data collection and design validation
  • Strong system level debugging and data analysis skills

For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice.

California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.

#LI-BL1